Graduate Theses and Dissertations
Iowa State University Capstones, Theses and Dissertations
2009
High bandwidth low power operational amplifier design and compensation techniques Vaibhav Kumar Iowa State University
Follow this and additional works at: https://lib.dr.iastate.edu/etd Part of the Electrical and Computer Engineering Commons Recommended Citation Kumar, Vaibhav, "High bandwidth low power operational amplifier design and compensation techniques" (2009). Graduate Theses and Dissertations. 10766. https://lib.dr.iastate.edu/etd/10766
This Thesis is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact
[email protected]
High bandwidth low power operational amplifier design and compensation techniques
by Vaibhav Kumar
A thesis submitted to the graduate faculty in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE
Major: Electrical Engineering Program of Study Committee: Degang Chen, Major Professor Randall L. Geiger Mani Mina
Iowa State University Ames, Iowa 2009 Copyright © Vaibhav Kumar, 2009. All rights reserved.
ii
TABLE OF CONTENTS
LIST OF FIGURES ..................................................................................................... iv LIST OF TABLES ....................................................................................................... vi ABSTRACT ................................................................................................................ vii CHAPTER 1. Introduction.............................................................................................1 1.1 Background ......................................................................................................... 1 1.2 Thesis Outline ..................................................................................................... 5 CHAPTER 2. Literature review of frequency compensation techniques ......................7 2.1 Introduction ......................................................................................................... 7 2.2 Feedback Circuit Theory .................................................................................... 7 2.3 Stability of Feedback Systems .......................................................................... 10 2.4 Basic Frequency Compensation Techniques of Operational Amplifier ........... 12 2.4.1 Parallel Compensation ................................................................................13 2.4.2 Pole Splitting – Single Miller Compensation (SMC) .................................13 2.4.3 Miller compensation with Zero Nulling Resistor .......................................16 2.4.4 Other Multistage Operational Amplifier Compensation .............................17 2.4.4.1 Nested Miller Compensation (NMC) and the Variants .......................17 2.4.5 Active Feedback and Indirect Compensation .............................................19 CHAPTER 3. Indirect feedback frequency compensation ..........................................21 3.1 Introduction ....................................................................................................... 21 3.2 Small Signal Analysis ....................................................................................... 21 3.3 Indirect Feedback using Cascoded Loads ......................................................... 27 3.4 Indirect Feedback using Cascoded Differential Pair ........................................ 28 3.4 Other Operational Amplifier Specifications ..................................................... 31 3.4.1 Slew Rate Limitations in Op Amps ............................................................32 3.4.2 Random Offset ............................................................................................33 3.4.3 Common Mode and Power Supply Rejection Ratio ...................................34 3.5 PreDesign Procedure Guidelines ..................................................................... 35 3.7 Indirect Feedback Design Procedure ................................................................ 38 3.7.1 Input Referred Thermal Noise Spectral Density .........................................38 3.7.2 Slew Rate ....................................................................................................39 3.7.3 Output Swing ..............................................................................................40 3.7.4 CommonMode Range ................................................................................40 3.7.3 Indirect Frequency Compensation and Miller Capacitor ............................40 3.7.6 Final Design Procedure ...............................................................................43 3.7 Figure of Merit .................................................................................................. 45 CHAPTER 4. ...............................................................................................................46 4.1 Introduction ....................................................................................................... 46 4.2 Design Example ................................................................................................ 46 Op Amp Specification..........................................................................................47
iii Op Amp Sizing ....................................................................................................48 4.2.1 Bias Generator ............................................................................................49 4.2.2 Bias Transistor Sizing .................................................................................50 4.3 Simulation Results ............................................................................................ 50 Simulated Results.................................................................................................52 Relevant Design Parameters ................................................................................53 Comparison of Pole Locations .............................................................................53 4.4 Alternative Indirect Feedback Compensation Scheme Results ........................ 54 Comparison of Alternative Indirect Feedback Compensation .............................54 4.5 Performance Comparison to Miller Compensation and Single Stage Amplifiers ....................................................................................................... 55 Comparison with Miller Compensation and Single Stage Amplifiers .................55 4.6 Performance Comparison to Literature............................................................. 56 4.7 Layout ............................................................................................................... 57 CHAPTER 5. CONCLUSIONS AND FUTURE WORK ...........................................60 APPENDIX A. Schematics ..........................................................................................62 BIBLIOGRAPHY ........................................................................................................65 ACKNOWLEDGEMENTS .........................................................................................69
iv
LIST OF FIGURES Figure 11 Supply voltage (Vdd) and threshold voltage (Vth) trends in future CMOS semiconductor processes technology (ITRS) [1] .............................................................. 2 Figure 12 Open loop gain trends in future CMOS process [1]................................................ 3 Figure 13 Transistor transition frequency (fT) trends in future CMOS processes [1] ............. 3 Figure 14 Number of stages required to achieve the DC gain requirement for 10 and 14 bit resolution settling. The figure shows number of cascaded stages required with employing any cascoding for 10 bit ADC settling. It also shown the number internal stages with wide swing cascoded stage required for a 14 bit resolution settling [1] ........ 4 Figure 21 General negative feedback system .......................................................................... 7 Figure 22 Basic negative feedback system ............................................................................ 10 Figure 23 Amplifier gain and phase versus frequency showing the phase margin ............... 11 Figure 24 Miller compensation of a twostage Op amp ........................................................ 13 Figure 25 Small signal mode for two stage amplifier with miller compensation.................. 14 Figure 26 New location of poles due to miller compensation ............................................... 15 Figure 27 Effect of RHP zero on the frequency response of two stage amplifier ................. 16 Figure 28 Miller compensation with series resistor............................................................... 16 Figure 29 (a) Nested Miller Compensation (NMC), (b) Reverse Nested Miller Compensation (RNMC), (c) Multipath Nested Miller Compensation (MNMC), (d) Nested GmCc Compensation (NGCC) .......................................................................... 18 Figure 210 (a) Active feedback frequency compensation (AFFC), (b) Transconductance with capacitance feedback frequency compensation (TCFC) ........................................ 20 Figure 31 Block diagram depicting Indirect Feedback Frequency Compensation ............... 21 Figure 32 Topology for common gate indirect feedback frequency compensation .............. 22 Figure 33 Small signal model for common gate indirect feedback frequency compensation .................................................................................................................. 22 Figure 34 A two stage Op Amp with cascoded loads. The compensation capacitor is connected to node A for indirect feedback. .................................................................... 28 Figure 35 A two stage Op Amp with cascoded differential pair. The compensation capacitor is connected to node A for indirect feedback. ................................................. 29 Figure 36 Small signal model for Op Amp with cascoded differential pair. The compensation capacitor is connected to node A. ............................................................ 29 Figure 37 Slew Rate limitation in Class A type amplifiers. In this case, during discharging the output is limited by the current source Iss2. While charging there is ideally no limitation. ....................................................................................................... 32 Figure 38 Class AB output stage improving the slew rate of the Op Amp during discharging phase. However the charging is still limited by the compensation capacitor being charged by Iss1 current source. ............................................................. 33 Figure 39 gm/Id and fT versus Vov (V0 ............................................................................... 37 Figure 310 Two stage amplifier with Class A output stage and Indirect Feedback Compensation ................................................................................................................. 38 Figure 41 Two Stage Amplifier with Class A/B output stage and indirect feedback frequency compensation ................................................................................................. 47 42 Supply Independent Bias Generator ................................................................................. 49
v Figure 43 AC Frequency Response of Indirect Feedback Compensation Amplifier ............ 51 Figure 44 Large Signal Transient Response of Indirect Feedback Compensation Amplifier ......................................................................................................................... 51 Figure 45 Closed Loop Transient Response of Indirect Feedback Compensated Amplifier 52 Figure 46 Floor planning for two stage amplifier with indirect feedback frequency compensation .................................................................................................................. 58 Figure 47 Layout of Two Stage Op Amp with Indirect Feedback Compensation ................ 59 Figure 51 Two Stage Op Amp with Common Gate Indirect Feedback Frequency Compensation ................................................................................................................. 62 Figure 52 Two Stage Op Amp with Indirect Feedback Frequency Compensation to PMOS cascode node ....................................................................................................... 63 Figure 53 Two Stage Op Amp with Indirect Feedback Frequency Compensation to differential pair (NMOS) cascode node .......................................................................... 64
vi
LIST OF TABLES Table 41 Two Stage Design Op Amp Specification.............................................................. 47 Table 42 AMI 0.5 C5N Process Parameters .......................................................................... 48 Table 43: Transistor Sizing for Indirect Feedback Op Amp ................................................. 48 Table 44 Simulated Results for Indirect Feedback Compensated Amplifier ........................ 52 Table 45 Relevant Design Parameters ................................................................................... 53 Table 46 Pole and Zero Locations obtained during Simulation ............................................ 53 Table 47 Comparison of Alternative Feedback Compensation ............................................. 54 Table 48 Comparison to Miller Compensated and Single Stage Amplifiers ........................ 55 Table 49 Comparison of Two Stage Op Amp Topologies .................................................... 56
vii
ABSTRACT The need for high bandwidth operational amplifiers (op amp) exists for numerous applications. This need requires research in the area of Op Amp bandwidth extension. The exploited method in this thesis uses a class of compensation called Indirect Feedback Frequency Compensation in which the compensation current is fed back indirectly from the output to an internal high impedance node, to extend the bandwidth of an Op Amp. Among various compensation methods for operational amplifiers, indirect compensation offers potentially large benefits in regards to power to speed tradeoff. The indirect compensated Op Amps can exhibit significant improvements in speed over traditional Miller compensated Op Amps and result in much smaller layout size and lower power consumption. However the technique has not been widely used in practice due to a lack of clear design procedure. This thesis develops an analytical description of how indirect compensation works and derives key trade off equations among various specifications. These results provide the insight needed for practically designing operational amplifiers with this technique. Based on the results, a stepbystep design procedure is proposed for an operational amplifier using indirect compensation. To demonstrate the proposed design procedure, a two stage Op Amp is designed. The Op Amp achieved a 2 MHz gainbandwidth product (GBW) driving a large capacitive load (100 pF). The GBW of the Op Amp was improved by a factor of 10 times compared to the miller compensation scheme. The amplifier documented in this thesis achieved a higher simulated figuresofmerit (FoMs) compared to the stateofart and can be directly used in integrated systems to achieve higher performance.
1
CHAPTER 1. INTRODUCTION 1.1 Background Operational Amplifiers (Op Amps) are an integral part in design of various analog and mixedsignal systems. Their applications extend from dc bias applications to high speed ADC/DAC’s and filters. General purpose Op Amps find their use in most analog subsystems, particularly in switched capacitor applications. In most of such systems, the overall system performance is strongly influenced by the Op Amp performance. With major enhancements in computer aided design (CAD) tools, advancements in semiconductor characterization and modeling, transistor scaling, and the progress of fabrication processes, the integrated circuit field is expanding rapidly. Integrated circuits once served the role of subsystem components, portioned at analogdigital boundaries, however they now integrate complete systems on a chip by combining both analog and digital functions [2].
Complementary metaloxide
semiconductor (CMOS) technology has been the mainstay in mixedsignal because it provides density and power savings on the digital side, and a good mix of components for analog design. However, continued scaling of CMOS processes has continually challenged the established paradigm for operational amplifiers design. Scaling down of CMOS feature sizes enable yet faster speeds, the supply voltage is scaled down to enhance device reliability and improve power consumption. The expression for a short channel MOSFET transition frequency (fT) and openloop gain (gm • ro) are given as [3] Equation 1.1 Equation 1.2
where VEB, L, gm and ro are the excess bias voltage, channel length, transconductance and output impedance respectively for a MOSFET.
2 As can be seen from Equations 1.1 and 1.2, scaling down of feature sizes results in a higher fT, and therefore faster operating transistors. However, this is achieved at the cost of a reduction in transistor’s open loop gain. Thus, amplifiers designed in smaller feature size processes exhibit larger bandwidths but lower open loop gain. Moving to lower feature size processes also requires reduced supply voltages. However, the threshold voltage of a transistor is not reduced by the same ratio in order to keep leakage currents under control. A direct result of this is the difficulty in using cascoding (vertical stacking of transistor to increase gain) transistors and other cascode based gain enhancement topologies.
Figure 11 Supply voltage (Vdd) and threshold voltage (Vth) trends in future CMOS semiconductor processes technology (ITRS) [1]
From Figure 11 it can be observed the upcoming process technologies in the future have continuous scaling down of analog VDD. However the threshold voltage is not scaling down with the same factor [1]. Also the scaling down of digital VDD is more aggressive in comparison to analog, which indicates the future holds even more challenge in integration of analog and digital designs.
3
Figure 12 Open loop gain trends in future CMOS process [1]
Figure 12 highlights the projection of openloop voltage gain drops from CMOS transistors. The open loop gain for submicron processes currently is at the order of 10’s which already poses significant design challenges. Furthermore, the future processes are not showing promising transistor matching data as the feature sizes reduce. Equation 1.3 gives the expression for threshold voltage mismatch (σth) given by[1] ·
Equation 1.3
.
Figure 13 Transistor transition frequency (fT) trends in future CMOS processes [1]
4 Figure 13 shows the trends in transistor transition frequency (fT) with CMOS process technology progression. From the above trends it is evident that designing a high gain operational amplifier in future CMOS processes is a challenging task. Now, for an N bit resolution ADC, the open loop dc gain (ADC) requirement is expressed as [4] 

·
Equation 1.4
where β is the feedback factor in the Op Amp architecture. For β = ½, which is the case in a R2R data converter and other various architectures the required open loop is given as [4] 

Equation 1.5
Therefore for a 10 and 14 bit resolution ADC, the open loop dc gain required from the Op Amp would be 4K and 16K respectively. Figure 14 illustrated the number of amplifier stages inside an Op Amp required to achieve sufficient Op Amp gain for 10 bit
Figure 14 Number of stages required to achieve the DC gain requirement for 10 and 14 bit resolution settling. The figure shows number of cascaded stages required with employing any cascoding for 10 bit ADC settling. It also shown the number internal stages with wide swing cascoded stage required for a 14 bit resolution settling [1]
5 settling requirements. It also depicts the number of internal stages required with wide swing cascoded structures to achieve sufficient gain for 14 bit settling requirements. The swing for a wide swing cascode is given as (2VDS,sat, VDD2VDS,sat), where VDS,sat is the saturation voltage for the transistor for a given bias [5]. With VDS,sat not reducing in the same fashion as the power supplies, it would become even more difficult to use a wide swing cascode itself. Figure 14 also depicts the needs and trends of future Op Amps architectures. It predicts that stepping into the next decade operational amplifiers with more than two stages would be needed to recover the dc gain. Also with the emerging low voltage, low power applications markets, such as cell phones and portable media devices, the required openloop dc gain can only be achieved b Op Amp with more than two stages. Applications of high gain operational amplifiers with more than two stages can be extended to comparators, sigma delta A/D, low distortion oscillators, multivibrators, and a host of others. This thesis presents development of novel highspeed, low voltage, lowpower, multistage Op Amp topologies which tremendously improve upon the stateofart. Also the improved Op Amp frequency compensation scheme, called indirect feedback compensation introduced in [6] is amply developed and presented. The indirect feedback compensation, when applied to multistage Op Amp design, solves many problems with techniques proposed in literature, and enables realization of extremely lowpower Op Amp topologies.
1.2 Thesis Outline The research presented in this thesis covers studies related to frequency compensation methods of operational amplifiers and low voltage low power analog circuit design. Each chapter presents the analysis of the problem and the development of the solution. A brief outline of each chapter is described below.
6 Chapter 2 covers the general background information for frequency compensation. The basics of feedback network theory and stability associated with negative feedback amplifiers are discussed. Basic frequency compensation techniques such as miller compensation are discussed and the limitations are analyzed. Novel and more recent techniques promising high performance are also discussed. Chapter 3 covers the analysis and development of the indirect feedback compensation strategy. An exact analysis of the strategy and a simplified analytical model for indirectly compensated Op Amps are presented. The potentials for the architecture are discussed and a design procedure is provided. Chapter 4 illustrates the application of the indirect feedback compensation. A two stage amplifier employing indirect feedback compensation is designed. The frequency compensation is then employed in traditional cascoded architecture to demonstrate the feasibility of the frequency compensation technique. Chapter 5 provides the conclusions drawn from the work presented in this thesis along with the directions for future research on this topic.
7
CHAPTER 2. LITERATURE REVIEW OF FREQUENCY COMPENSATION TECHNIQUES 2.1 Introduction Feedback is a powerful technique that finds wide application in analog circuits. The high gain from amplifiers ensures the closed loop transfer characteristics with negative feedback are independent of the Op Amp gain. However, an adequate gain is a key requirement to utilize this technique.
2.2 Feedback Circuit Theory Figure 21 shows a general negative feedback system [7], where H(s) and G(s) are called the feedforward and the feedback networks, respectively. Since the output of G(s) is equal to G(s)Y(s), the input to H(s), called the feedback error and output are given by
Equation 2.1 .
Figure 21 General negative feedback system
8 Thus .
The quantity H(s) is the open loop transfer function and Y(s)/X(s) is the closed loop transfer function. H(s) represents the operational amplifier and G(s) is a frequency independent quantity. In other words, a fraction of the out signal is sensed and compared with the input and generating an error term. In negative feedback system, the error term is minimized, thereby making the output of G(s) an accurate copy of the input and hence the output of the system is an accurate replica of the input [7]. Feedback circuits provide gain desensitization, i.e. the closed loop gain is much less sensitive to the open loop gain [5]. This property can be quantified as following
.
where A and β are the low frequency gain of H(s) and G(s) respectively, and the dc gain Aβ
1. It can be noted that the closedloop gain is determined, to the first order by the
feedback factor, β. More importantly, even if the openloop gain, A, varies by a factor of 2, Y/X varies by a small percentage because
1/(Aβ)
1. The quantity Aβ is called the loop
gain. The loop gain plays an important role in feedback system. As seen from Equation 2.4 that the higher Aβ is, the less sensitive Y/X will be to the variation in A. From another perspective, the accuracy of the closedloop gain improves as the open loop gain or feedback factor are maximized. However, as the feedback factor β is increased, the closed loop gain decreases Y/X 1/β, so there is an inherent tradeoff between precision and the closed loop gain.
9 Negative feedback also exhibit effects on the bandwidth of the amplifier. Certain configurations of a feedback amplifier extend the closed bandwidth of the amplifier beyond the open loop amplifier. Assuming the feedforward amplifier in Figure 21 has a single transfer function as given below .
where Ao denotes the low frequency gain and ωo is the 3dB bandwidth. The transfer function of the closed loop system can then be expressed as
.
The numerator in Equation 2.6 is the closed loop low frequency gain equivalent Equation 2.4.
The denominator provides the location of the pole at
1
Comparing this to Equation 2.5 the 3dB bandwidth has increased by a factor of 1
. .
The extended bandwidth comes at the cost of proportional reduction in the gain as the product of gain and bandwidth is a constant for such an operational amplifier. Another very important property of negative feedback is the suppression of nonlinearity in analog circuits [8]. Nonlinearity can be regarded as the variation of the small signal gain with the input dc level. Negative feedback keeps the overall closed loop gain nearly constant and almost independent of the amplifier open loop gain. Therefore negative feedback circuits reduce distortion resulting from the change in the slope of the amplifier transfer curve. Mathematical analysis of the effect of a feedback system on nonlinearity of a circuit is very complex and can be found in [3, 5].
10
2.3 Stability of Feedback Systems Negative feedback finds diverse application in processing of analog signals. The properties of feedback described in section 2.2 allow precise operations by suppressing variations of the open loop characteristics. However, feedback systems suffer from potential instability, that is, they may oscillate.
Figure 22 Basic negative feedback system
Considering the negative feedback system shown in Figure 22 the closed loop transfer function can be written as .
If βH(s = jω1) = 1, then from observing Equation 2.6 the gain goes to infinity and the circuit starts to amplify its own noise until it eventually begins to oscillate. This condition can be expressed as 

.
°
.
which are called the “Barkhausen’s Criteria”. It can be observed that the total phase shift around the loop at ω1 is 360° because the negative feedback introduces itself a 180° of phase shift. The 360° of phase shift is required for oscillation as the noise has to shift by 180°
11 to be in phase with the signal to add. The other condition on loop gain being unity or greater is required to enable the growth of the oscillation amplitude. The condition necessary and sufficient for negative feedback stability is that all the poles of the feedback system are have a negative and real part. This from Laplace’s criteria translates to the poles being on the left half side of the plane. It may be difficult to analyze the stability of a complex system from looking at the closed loop poles of the system, since finding the zeros of the denominator 1+βA(s) may be complicated. It would be therefore much useful if the closed loop stability could be predicted from observing the open loop response of the amplifier. The concept of phase margin for an open loop amplifier is good indicator of the stability of the closed loop system. From the Nyquist criterion “If A(jω) >1 at the frequency where ph A(jω) = 180°, then the amplifier is unstable.” Figure 23 shows the loop gain magnitude A(jω) is unity at frequency ωo. At this frequency the phase of A(jω) has not reached 180° for the case shown, and using the Nyquist criterion state we conclude that this feedback loop is stable.
Figure 23 Amplifier gain and phase versus frequency showing the phase margin
12
As A(jω) is made closer to unity at the frequency where ph A(jω) = 180°, the amplifier has a smaller margin of stability, and this can be specified in two ways [9]. The most common is the phase margin, which is defined as follows: Phase margin = 180° + (ph A(jω) at frequency where A(jω) = 1). The phase margin is indicated in Figure 23 and must be greater than 0° for stability. [3]
2.4 Basic Frequency Compensation Techniques of Operational Amplifier The single stage amplifiers are inherently stable and typically have excellent frequency response assuming the gain bandwidth is ten times higher than the single pole. However, single stage amplifiers suffer from low dc gain and is even less for submicron CMOS transistors. In general, Op Amps require at least two gain stages which introduce multiple poles in the frequency response. The poles contribute to the negative phase shift and may cause ∠ FA to reach 180° before the unity gain frequency. Therefore due to insufficient phase margin the circuit would oscillate. Thus the amplifier circuit needs to be modified to increase the phase margin and stabilize the closed loop circuit. This process is called “compensation”. By intuition, two different approaches may be taken to stabilize the loop. The more straightforward approach way is make the gain drop faster in order for the phase shift to be less than 180° at the unity gain frequency. This approach achieves stability by reducing the bandwidth of the amplifier and the most popular pole splitting method uses this procedure. Another compensation method pushes the phase crossover frequency out by decreasing the total phase shift. In this particular case the total number of poles needs to be reduced while still maintaining the dc gain. This is achieved by introducing zeros into the open and close loop transfer function to cancel the poles, or using feedforward paths to improve the phase margin without narrowbanding the bandwidth as much as the pole splitting does.
13
2.4.1 Parallel Compensation Parallel compensation is a classical way to compensate the Op Amp. A capacitor is connected in parallel to the output resistance of a gain stage of the operational amplifier to modify the pole. It is not commonly used in the integrated circuit due to the large capacitance value required to compensate the Op amp, which considerable die area.
2.4.2 Pole Splitting – Single Miller Compensation (SMC) The most widely used compensation technique in analog circuit and systems design is undoubtedly pole splitting. A miller capacitor is used to split the poles, which causes the dominant pole to move to a much lower frequency and thus reducing the bandwidth and providing ample stability. This method is featured in the original 741/101 bipolar Op Amps designed by Robert Widlar and was widely implemented henceforth [10].
Figure 24 Miller compensation of a twostage Op amp
Figure 24 shows the block diagram of a twostage operational amplifier employing Miller Compensation or Direct compensation technique. The Op Amp consists of an input differential pair stage with gain A1. The second stage (output stage) is biased from the output of the differential stage and driving a large capacitive load. Before the compensation, the poles of the two stage cascade are given as and
, where Rk and Ck are the resistance and capacitances at those nodes. In order to
14 achieve dominant pole stabilization of the Op amp, Miller compensation is used to perform pole splitting. A compensation capacitor is place between the output of the amplifier and the output of the first stage as shown Figure 24. The compensation capacitor seen at node A is then (1+A2)Cc due to the miller effect [8]. This kind of compensation splits the two pole apart as shown in Figure 26. The dominant pole is move to a much lower frequency, thereby reducing the bandwidth, while the nondominant pole is moved to a higher frequency. However the miller capacitor also introduces a right half plane zero due to the feedforward current from the output of the internal stage to output of the amplifier. Figure 25 shows the small signal model
Figure 25 Small signal mode for two stage amplifier with miller compensation
The small signal transfer function for the two stage amplifier with miller compensation is given as .
The RHP zero is located at .
The dominant pole is located at .
15
The non dominant pole is locate at .
The overall dc gain of the amplifier from Equation 2.9 is
, and the
unity gain frequency for the amplifier is fun = gm1/2πCc. The pole splitting due to the miller compensation is shown below in Figure 26.
Figure 26 New location of poles due to miller compensation
Figure 27 shows the frequency response of the Miller compensated twostage amplifier. It can be observed that the RHP zero degrades the phase response of the open loop amplifier. The phase contribution due to the RHP zero is
tan
which leads to
instability when the second pole moves closer to the unity gain frequency (fuf). In Figure 27 the RHP zero not only flattens the magnitude response due to the dominant pole but also degrades the phase make it difficult to stabilize the amplifier. This RHP zero can be eliminated by blocking the feedforward compensation current, while allowing the feedback component of the compensation current achieve pole splitting [11]. Several methods have been suggested in [5] and [12] to cancel the RHP zero which will be discussed in the next section.
16
Figure 27 Effect of RHP zero on the frequency response of two stage amplifier
2.4.3 Miller compensation with Zero Nulling Resistor A common method to cancel the RHP zero is by using a series resistor with compensation capacitor as shown in Figure 28. With the addition of series resistor [13], the new location of the zero is .
Figure 28 Miller compensation with series resistor
17 Observing Equation 2.13 the location of zero can be controlled with the value of the series resistor Rz. For Rz=1/gm2 the zero moves to infinity and for Rz greater than 1/gm2 the zero moves to the LHP and help improving the phase margin. This addition of the series resistor does not move the location of the p1 and p2, however introduces a third pole at which is far away from the other two poles. The resistor Rz can be implemented using a transistor in triode region, and can be made to track the value of 1/gm2 and cancel the RHP zero.
2.4.4 Other Multistage Operational Amplifier Compensation As discussed section 1, with supply voltages declining, the singlestage cascoded based architectures have become unsuitable for some applications because of the limited signal swing capability. As a result, designers have started looking for alternative architectures to overcome the drawbacks of single stage amplifiers. One alternative is to recover the gain by cascading stages. However, as observed in the previous section, cascaded structures are unstable in nature, and simple miller compensation technique analyzed in the previous section reduces the bandwidth of the amplifier significantly. In the recent times new architectures have been proposed to tackle this issue [14]. This section briefly describes the recent developments in the area and bring upfront the pros and cons of each architecture.
2.4.4.1 Nested Miller Compensation (NMC) and the Variants Multistage amplifiers have more poles and zeros compared to the single stage amplifier. Thus the frequency response of these multistage amplifiers is much more complex. As a result, multistage amplifiers suffer from closed loop stability issues. Frequency compensation attempts to stabilize the amplifier, but reduce the bandwidth of the amplifier significantly, thus amplifiers with more than 3 stages are hardly considered. Single Miller Compensation as described in previous section can be effectively used to stabilize two stage amplifiers. The concept can be extended to multistage amplifier by nesting the miller
18 compensation strategy. The technique is called Nested Miller Compensation (NMC) is described in [1517] and is shown in Figure 29(a). There are certain drawbacks related to the NMC approach. A total of N1 capacitors are needed to stabilize an N stage amplifier. The necessity to drive the compensation capacitor along with the capacitive load requires the output stage to have a high transconductance to attain wide bandwidth and high slew rate. To address the reduction in bandwidth many variants of the NMC have been proposed. Shown in Figure 29, Reverse nested miller compensation (RNMC) [18], Multipath nested miller compensation (MNMC) [16], Nested GmCc compensation (NGCC) [19] are some of the alternatives to recover the bandwidth.
Figure 29 (a) Nested Miller Compensation (NMC), (b) Reverse Nested Miller Compensation (RNMC), (c) Multipath Nested Miller Compensation (MNMC), (d) Nested GmCc Compensation (NGCC)
19 RNMC improves the bandwidth by making the second stage have a negative gain and the output stage having a positive gain [18]. This allows the miller capacitor C2 being wrapped around the second stage and thus avoid the loading of compensation capacitor on the output in comparison to NMC. The variation between the NMC and MNMC is that the latter has a feedforward path which is also a high speed path. The feedforward path introduces a zero which can be used to cancel one of the nondominant poles and extend the bandwidth. This significantly increases the complexity of the design and the extra path increases the power and chip area as well. Further polezero cancellation need to be accurate to exploit the benefits of the architecture. It has also been well documented about the poor transient response for a pole zero doublet [16]. The difference between NGCC and MNMC is that the idea of feedforward stage is replicated for each stage. The topology is much easier to analyze and understand as the transfer function is much simpler in comparison to MNMC. The basic idea behind all of the above variants of NMC is to introduce a zero to cancel one of the non dominant poles. All these topologies however still rely in the miller capacitor to split the dominant and non dominant pole from the load capacitor. Thus the miller capacitor scales larger with increasing capacitive load drives. The next section address a new class of topology used for driving large capacitive loads and show potential for having bandwidth even larger than single stage.
2.4.5 Active Feedback and Indirect Compensation A newer class of frequency compensation driving large loads was proposed in [13] and [14]. As shown in Figure 210(a), the technique is a variant of miller compensation between nodes B and node Vout. A form of indirect compensation is used here to feedback the compensation current from node Vout to node A. In the block diagram, the high gain
20 block (HGB) is the cascade of stages to achieve the high dc gain, while the high speed block (HSB) is to provide the high frequency response and stability. Another variation of indirect compensation is presented in [20] by Sansen. Figure 210(b) shows the Transconductance with Capacitance feedback frequency compensation (TCFC). Both architectures promise in providing stellar frequency response due to the reduction of miller capacitance size required by these topologies. Furthermore the compensation current for the internal amplifier is feedback internally from Vout to Vs in AFFC and in TCFC from Vout to node B. A generalized indirect feedback compensation scheme is proposed and analyzed in detail in this thesis. The compensation scheme enables in achieving very lowpower lowvoltage multistage Op Amps with improved stability.
Figure 210 (a) Active feedback frequency compensation (AFFC), (b) Transconductance with capacitance feedback frequency compensation (TCFC)
21
CHAPTER 3. INDIRECT FEEDBACK FREQUENCY COMPENSATION 3.1 Introduction As introduced in the previous section, the class of compensation in which the compensation current is fed back indirectly from the output to the internal high impedance node is called Indirect Feedback Frequency Compensation. Here the compensation capacitor is connected from the output to an internal low impedance node, which indirectly feeds the current to the high impedance node A. Figure 31 depicts the block diagram of the Indirect Feedback Frequency Compensation. In the block diagram the effective low impedance attached at node A is detected by Ri.
Figure 31 Block diagram depicting Indirect Feedback Frequency Compensation
3.2 Small Signal Analysis In order to gain insight of the indirect feedback frequency compensation technique, a detailed analytical and mathematical analysis is required. Figure 32 shows the topology of the two stage Op Amp. A common gate amplifier M6 is used to provide the compensation current indirectly to the high impedance node V1. The common gate amplifier isolated the node V1 from the compensation capacitor and thus does not load the out of the first stage.
22
Figure 32 Topology for common gate indirect feedback frequency compensation
To develop an understanding of the performance potential the above topology provides a small signal analysis needs to be performed. The small signal model for the above topology is shown in Figure 33.
Figure 33 Small signal model for common gate indirect feedback frequency compensation
The model used in the small signal analysis has three nodes, and thus there dependent variables, Vd, VA, and Vout. Also the variable Vd is the differential input Vp – Vn. For the common gate amplifier a Tmodel is used, and gmcg and roc represent the transconductance and impedance of the common gate amplifier respectively. The impedance
23 RA and CA represent the parasitics at the internal low impedance node VA. The nodal analysis can be thus done as shown below: 0
.
0
.
0
.
On simultaneously solving the above three equation, the transfer function from Vout to Vd can be expressed as
.
The third order transfer function has three poles and single left half plane zero. The exact values of the coefficients are given below: 1 1
.
5 2
1
0
.
–
1
1
0 1
.
5
.
1 5 2
1
5 2 1
1
1 1
1 1 2
1 2
2 2
.
1
2 2 3
1 1 1 2
2 1 1 1
2 1 1
1 2 2
. .
24 In the above expression Rk and Ck are the impedance at respective nodes. Simplifying the above expression by making the assumption gmkRk
1, and CL, Cc
C1, CA, the above
can be expressed as 0
.
1
.
1
0 1
1
5 2 1
1
2
3
. .
2 1 1
2 2
1
1
.
1 1 2
.
From the above simplified expressions the location of the zero from Equation 3.4 can be evaluated as shown below. Evidently, the zero is in the left half plane.
.
Further, assuming the pole p1
p2, p3 the dominant real pole is given as 1
.
Now for s>> p1, the denominator of the transfer function D(s), can be approximated as 1
1
.
From Equation 3.21 the non dominant poles can be derived. Assuming the two non dominant poles are real and spaced wide apart when when
4
. The above condition is satisfied
25
4
4
.
The above condition states that a large transconductance is required for common gate amplifier. However, when the above condition is met the non dominant poles relocate to the following locations .
1 
.
The unitygain frequency of the Op Amp is given as:
f
ω 2π
p AV 2π
g 2πCC
.
From Equation 3.23 the nondominant pole, when using indirect feedback compensation, is located at
C CL C
while the second pole for Miller compensation was located at
C
CL
.
By comparing the two equations, we can examine that the second pole, p2, has moved further away from the dominant pole by a factor of approximately Cc/C1. Furthermore the LHP zero adds to the phase response near the unity gain frequency and thus improves the phase margin. The overall transfer function of the system can be express as 1 ·
1 1
·
1
Thus the condition on gmc can be rewritten as the following
.
26
4
 
·
4
.
.
The above argument implies that now we can achieve pole splitting with a much lower value of compensation capacitor (Cc) and a lower value of second stage transconductance (gm5). Conversely, lower value for gm2 translates into lower power as the bias current can be reduced. On the other hand, we can achieve higher unity gain frequency for the Op Amp without affecting stability and hence obtain a higher speed amplifier or drive a larger load capacitor for a given phase margin[21]. Analytically the reason the nondominant pole shifted to a higher frequency is because the compensation capacitor now does not load the first stage output. Also Equation 3.22 is a key requirement for this architecture as it expresses the condition with respect to the transition frequency (fT) of transistor M6 and M5 the common gate amplifier and output stage respectively. It signifies that the indirect path has to be much faster than the output stage which thus relocates non dominant pole to higher frequency and thus improving the unity gain frequency. Blatantly observing, indirect feedback compensation can lead to the design of Op Amps with significantly lower power, higher speed and lower layout area. Observing Equation 3.24, the location of the third nondominant pole is further away from the second pole as long the gmcg is large, and R1, C1 are small. Thus the third non dominant pole does not affect the phase margin. Now considering if the condition in Equation 3.22 is not met then the poles are complex in nature and are defined below. The real part of the conjugate pole pair is given by
27 · ,
·
.
1
The damping factor for the complex poles is 1 2
2
.
Also it can be observed that the ,
.
The non dominant pole is much further away from p1 as long as the transconductance of the common gate amplifier is large and the parasitic at node 1 is kept low.
3.3 Indirect Feedback using Cascoded Loads Many operational amplifiers commonly have cascoded first stage or subsequent cascoded stages to obtain a high dc gain. When using a cascoded first stage, a low impedance internal node is easily available. This low impedance internal node can then be used to indirectly feedback the compensation current. Figure 34 depicts an implementation of an indirect feedback using cascoded current mirror load. In this topology the common gate amplifier is embedded inside the cascoded current mirror load. Node A forms the low impedance needed for indirect feedback current to node V1. The small signal mode for the following topology is the same as in Figure 33, where the common gate amplifier is the cascode transistor Mc2. Similar to the common gate amplifier analyzed in the previous section, the LHP zero and the three poles are given by Equations 3.193.24, where gmcg is the transconductance of the cascode transistor gmc2. The cascoded loads topology saves area and power as an additional common gate stage is not required. However, the reduction in power comes at the cost of flexibility choosing the transconductance of gmcg, which controls the location of the LHP zero.
28
Figure 34 A two stage Op Amp with cascoded loads. The compensation capacitor is connected to node A for indirect feedback.
3.4 Indirect Feedback using Cascoded Differential Pair Other than a cascoded current mirror load, a cascoded differential pair could also be used to feedback the compensation current indirectly. Figure 35 shows the schematic for implementing such architecture. The compensation capacitor is connected to the low impedance node A. However, this topology is not the same as the cascode current mirror load, as the common gate amplifier is not isolated from the input. This leads to both an indirect feedback current, as well as a feedforward current through the compensation capacitor to the output. The feedforward current can only be eliminated if all the current at the source of Mc2 is passed through the drain and not through the compensation capacitor, which is only possible when the transconductance of Mc2 is infinite.
29
Figure 35 A two stage Op Amp with cascoded differential pair. The compensation capacitor is connected to node A for indirect feedback.
The small signal model for the two stage amplifier with cascoded differential pair is shown below in Figure 36. A small signal is required to understand the implications of the feedforward current through the compensation capacitor.
Figure 36 Small signal model for Op Amp with cascoded differential pair. The compensation capacitor is connected to node A.
30 On doing the nodal analysis as in previous section, the Kirchhoff equations can be written as: VA RA
V
VA sCA
V R
VA V R
V
gm V
V
VA V r
sC
VA
V
V sC
sC VA
0
.
0
r sC V
V
VA
.
0
.
Solving the above simultaneous equations, the below small signal transfer function is obtained. .
The coefficients are given as: 1 1
.
5 2
1
0 1
–
2
–
. 1
⁄
1
⁄
.
5
1
0 1
5 2
1
5 2 1
1 1
1 2
3
.
1
1 1
2
.
2 1
1 1 2
1 2
2
1 2
.
2 2 1 1 1
2 1
1 2 1 1
2
.
1 1 2
The above expressions can be simplified by making the approximations that gmkRk 1, and CL, Cc
C1, CA. The simplified has the same denominator as Equation 3.21. However,
the numeration coefficients and the locations of the two zeros are expressed below:
31
,
2
1 
1 4
.

From Equation 3.42 it is can be noticed that the zeros are real and one of the zero is in the LHP while the other in RHP. 2
2
1  1 
1 4
.
 1
4
If assuming the condition
.


, the locations of the zeros can be
simplified as gm gm CC
.
gm gm CC
.
The approximate pole locations for this topology are exactly the same as derived for cascoded load indirect compensation. Furthermore, the location of the right half plane is so far away from the unity gain frequency, that it is unlikely it would degrade the Op Amps frequency response. Considering the poles of the system are complex, then from Equation 3.28 it can be seen the poles are at the same frequency as the zero. Thus the complex poles and zero are clustered, and can be approximated by two real left half plane poles and one right half plane zero.
3.4 Other Operational Amplifier Specifications Apart from the speed of the amplifier, there are other specifications that need to be addressed. This section provides an overview and common techniques used in literature to improve and enhance those specifications.
32
3.4.1 Slew Rate Limitations in Op Amps Op Amps used in feedback circuits exhibit a largesignal behavior called “slewing”. Slew rate represents the maximum rate at which a capacitive load is charged and discharged. The slew rate is thus defined as dt
I CL
.
The Op Amp architectures presented in previous sections, Figure 32, 34, 35, are all Class A type amplifiers. In Class A Op Amps the charging and discharging of the load capacitor is provided by the fixed current source. This fundamentally limits the slew rate of the amplifier. Figure 37 shows the slew rate limitations in these amplifiers. During charging of the capacitor CL, there is no slew rate limitation, as the transistor gate M5 is completely pulled, and the transistor sources current following the square law model. However while discharging the capacitor, the fixed current source Iss2 limits the rate. The discharging slew rate is thus given by
, where Iss2 is the output bias current [22]. Indirectly this
implies that in class A type Op Amps, higher current need to be burned for achieving high slew rate. Furthermore, driving large loads of 100pf and above requires an extremely large quiescent current. To solve the problem of high power requirement for slew rate, Class AB type output stages can be designed. This is explained in Figure 38. VDD
VDD M3
M3
M4
V1 Vbb
Mc1
V1
M5
Vbb
Mc1
Mc2 Cc
M1
M4
M5 Mc2 Cc
Vout
M2
CL
M1
M2
SR = inf
Vout CL
SR = Iss2 CL
Figure 37 Slew Rate limitation in Class A type amplifiers. In this case, during discharging the output is limited by the current source Iss2. While charging there is ideally no limitation.
33 The Class AB output stage is realized by have a floating current source biased between the output stages transistors behaving like a push pull [3]. The floating current source acts like a battery turning M5 on hard and turning off M6 when charging, and turning M6 on and turning off M5 during discharging. VDD M3
M4
VDD M3
Mpcasc
V1 Vbb
Mc1
Vbb
Mc1
Iss2
Mc2
Mpcasc
V1
M5
Cc M1
M4
Iss2
Mc2 Cc
Vout
M2
M5
CL
M1
M2
CL
M6
Mncasc
Vout
M6
Mncasc
It may38 seem the Class actionthe hasslew norate slew rateOplimitation, the transistor the Figure Classthat AB output stageAB improving of the Amp duringasdischarging phase.inHowever the charging is still limited by the compensation capacitor being charged by Iss1 current source. output source and sink currents according to the square law model. However, this is not true,
as a new slew rate limitation appears during charging as shown in Figure 38. The capacitor Cc needs to be charged, and the first stage current source provides the current to charge it. Thus during charging the slew rate is given by
. However this slew rate is much
higher than the Class A type, as Cc is much smaller than the load capacitor CL. Furthermore, indirect compensation achieve higher slew rate in comparison to miller compensation as the Cc value is much smaller.
3.4.2 Random Offset Offset is an important dc specification for an operational amplifier as it limits the dc precision of the amplifier. Suppose the differential pair of Figure 32 is to amplify a small input voltage. Then in a cascade of directcouple amplifiers the dc offset may experience so much gain that it drives the later stage into the nonlinear operation. More importantly the effect of offset limits the performance of an amplifier if it is used to determine whether an
34 input signal is greater or less than a reference. In such a case the inputreferred offset voltage imposes a lower bound on the minimum VinVREF. Offset for operational amplifier architecture shown in Figure 32 has been previously derived in [5]. The expression below is the random inputreferred offset voltage ∆ ,
2 ∆ ,
2 ,
∆
,
.
∆
,
. .
,
Observing Equation 3.48 and 3.49 it can be noticed increasing the input pair area and current load area reduces the random inputreferred offset voltage. Other techniques such as resistive degeneration can be used to reduce the contribution of the current load offset (VOS,P). Offset cancellation techniques as in [23] can also be implemented to cancel and reduce the input referred offset specification.
3.4.3 Common Mode and Power Supply Rejection Ratio An important aspect of the differential amplifier is its ability to reject a common signal applied to both inputs. Often, in analog systems, signals are transmitted differentially, and the ability of an amplifier to reject coupled noise into each line is very desirable. Thus common mode rejection ratio (CMRR) is an important specification for an Op Amp. The expression of common mode gain has been derived in [3, 8] 1
1
,
2 20
20
2 ,
. ,

·2
,
.
35 The larger the CMRR better the performance of the amplifier. Many techniques such as high impedance current sources and regulated circuits have been proposed in literature to improve the common mode performance of the Op Amp. Power supply rejection ratio (PSRR) is a parameter of high importance in MOS amplifier design [3, 8]. With high integration of analog and digital systems, separate analog and digital supply buses are often run on chip. However it is still hard to avoid some coupling of digital noise into the analog supplies. Furthermore, many systems employ switching regulators which introduce power supply noise into supply voltage lines. The expression for PSRR is given in [5] as 
.
The basic circuit of Figure 32 exhibits very poor high frequency rejection from the positive supply rail. The main reason is that as the applied frequency increases, the impedance of the compensation capacitor decreases, effectively shoring the drain of M5 to its gate for ac signals. The gain from the positive supply to the output approaches unity and stays there out to very high frequencies. Several alternative amplifier architectures have evolved which alleviate this problem; one such is the proposed indirect feedback frequency compensation using a common gate cascode. The resulting positive PSRR at high frequencies is greatly improved. Others include sub regulated power supply rails which also provide extremely good PSRR performance.
3.5 PreDesign Procedure Guidelines This methodology is intended for lowpower analog and digital signals where the weak as well as moderated inversion regions are often used because they provide good compromise between speed and power consumption. The gm/Id ratio is indeed a universal characteristic of all transistors formed by the same process.
36 MOS transistors are either in strong inversion or in weak inversion. Mainstream methods assume generally strong inversion and use the transistor gate voltage overdrive (VOV) as the key parameter, where VOV = VGSVt. If we consider a simple common source amplifier, the power and bandwidth are given by the following equations 1 2
.
3 2
.
With the assumed fixed design specifications, and a given technology (μ, Lmin), both power and bandwidth of our circuit are completely determined by the value of VOV. Making VOV small to save power also means that we lose bandwidth. This makes intuitive sense since VOV
.
With gm and L fixed, smaller VOV translates into bigger (wider) device, and thus large Cgs. So it can be concluded that VOV is not
a good design parameter. What we really
want from MOS transistor is •
Large gm without investing much current
•
Large gm without large Cgs To quantify how good of a job our transistor does, we can therefore define the
following “figure of merits (FOM)”. •
Tranconductor Efficiency: .
•
Transit Frequency: .
37 Figure 39 shows the Transcoductor Efficiency (gm/ID) versus the Vov (over drive voltage) of the transistor with fixed W/L ratio and varying lengths. From the graph it can be inferred for AMI 0.5μm CN process to achieve optimal transconductor efficiency the over drive voltage from the transistor should be between 0.10.2V. After 0.4V the increase in gm with increase current is not efficient. Thus if the VOV of the transistor is high, then increasing the current would only increase the gm of the transistor marginally. Similarly increasing the size would give a marginal increase in transistor transconductance. Figure 39 also shows the fT vs Vov, and for obtaining the highest fT minimum transistor length (0.6μm) should be used in the design. A tradeoff is seen between the transconductance efficiency and transit frequency (fT). Increasing the overdrive voltage higher speed transistor, however the transconductance efficiency is poor. The figure of merits should always be kept in mind during designing an amplifier for a particular process.
30
gm/Id and fT vs Vov L = 0.6μm
25
1E+12
1E+11
20
15
fT
L = 0.9μm
10
1E+09
L =1.2μm 100000000
5
10000000
0 ‐0.07409 ‐0.04349 ‐0.01289 0.01771 0.04831 0.07891 0.10941 0.14001 0.17061 0.20121 0.23181 0.26241 0.29301 0.32361 0.35391 0.38491 0.41491 0.44591 0.47691 0.50691 0.53791 0.56791 0.59891 0.62991 0.65991 0.69091 0.72091 0.75191 0.78291
gm\Id
1E+10
Vov (V) Figure 39 gm/Id and fT versus Vov (V0
38
3.7 Indirect Feedback Design Procedure This section provides a guideline for designing amplifiers with indirect feedback compensation method. The schematic for this particular design procedure is shown in Figure 39. The architecture is a two stage single ended Op Amp with a Class A output stage. A common mode feedback is provided to bias the first stage PMOS current load.
Figure 310 Two stage amplifier with Class A output stage and Indirect Feedback Compensation
3.7.1 Input Referred Thermal Noise Spectral Density The procedure starts with the thermal noise requirement for the Op Amp. Neglecting the flicker noise requirement, which contributes to the low frequency noise spectrum, the input referred noise voltage can be expressed as shown in Equation 3.59. 2·4
2 3
1 ,
1
,
.
,
To minimize noise, we assume gm3,4 < gm1,2 (which can be easily met) and calculate the transconductance gain of transistors M1,2 from Equation 3.60 ,
16 3
.
39 Input referred noise is sometimes not a critical performance specification. In those cases, a more relaxed input referred noise voltage can be calculated to obtain the input pair gm1,2. This requirement comes from comparing the thermal noise of the capacitor at the output over the bandwidth of the amplifier. This gives the following requirement
.
The input referred noise can then by a factor of 45 larger than the value of expression 4~5 ·
in Equation 3.61. Therefore approximately
. The larger the noise
specification, the smaller the transconductance of the input pair is required.
3.7.2 Slew Rate The slew rate performance of the amplifier is dependent on the transient response of both the output of the differential stage and the output of the Op amp, to which we will refer internal and external slew rate respectively. The external slew rate is characterized by the Class AB output stage transient dumping capability, which is described in section 3.4. The internal slew rate is defined by the equation: 2
,
.
2
Combing Equation 3.60, 3.62 and
,
, the transistor size for the
differential pair can be calculated to be: , ,
4
. ,
40
3.7.3 Output Swing By defining
as the Op Amp headroom voltage at output i.e., .
According to Figure 311 it is easy to show that .
3.7.4 CommonMode Range Defining
as the Op Amp head room voltage of the input commonmode range,
i.e., .
According to Figure 311 it is easy to show that ,
.
3.7.3 Indirect Frequency Compensation and Miller Capacitor Recalling the expression from 3.19 3.25 helps in analyzing the frequency response of an amplifier with indirect feedback frequency compensation. These expressions are recollected below form easier analysis. Dominant Pole:
Further if the condition
1
is met, then two nondominant real poles and
one left half plane zero is obtained from the transfer function, given below:
41 1  Finally the unity gain frequency is obtained by f
p AV 2π
ω 2π
g 2πCC
The compensation capacitor then can be calculated to be: g 2π f
.
Moving forward, making the following assumptions:        
·
1
.
1
1
.
Assumption in Equation 3.57 is valid because to have real poles for the system (Equation 3.22) gmc > gm2 by a factor of 4Cc/C1 which is much greater than one, and the geometric mean of C1CL is larger than Cc2. Nevertheless, it should be verified these ratios are greater than one during the design, as the system is modeled on the above assumptions. The equations 3.693.70 ensure that the system behaves as single dominant, and single nondominant pole, and GBW ≈ UGF. Thus Vout/Vin can be reduced to V V
ω s
1 1
s p
.
Following Pennisi [24] constraints and design strategies for sizing common gate amplifier M5 can be developed. The phase margin with 100% feedback can be shown to be  
.
42 .
The above equation 3.73 helps in sizing the transistor M5. Equation 3.71 also provides insight regarding the higher power saving achieved from the indirect feedback compensation. The factor C1/CC is less than one significantly and thus gm5 is reduced, indirectly less power required. Another degree of freedom, the current in M5, is available if a class AB output stage is implemented. There is flexibility in achieving the gm5 requirement by spending area or current. The transistor size of M5 can be decided by solving the following equations: 3 2
.
2
.
3
To obtain a high speed output stage L5 = Lmin, as seen from Figure 39. Simultaneously it should be verified if output swing requirements from Equation from 3.65 are met. Also it should be made sure that the transistor is not in subthreshold operation and thus Veff5 should be greater than 50mV. Output stage current can be decided by performing tradeoff between area and power tradeoff for the common gate stage and output stage. Reconsidering the Equation 3.22 it can be approximated how much larger gm5 is in comparison to gm6.
4
4
.
The geometric mean of C1CL is less than one and the total factor is about 0.5~2. Thus to the first order approximation gm6 ≈ (28)gm5. Thus the current between the common
43 gate stage and the output stage can be split to a ratio 2~4. The output stage current and M5 width can be calculated as following:
2~4 2
.
.
Finally the transistor size and current requirement in the common gate can be determined using Equation 3.22 for achieving real poles. 4
. .
4
3.7.6 Final Design Procedure A design step for twostage Op Amp (Figure 311) can be constructed as follows: Step 1.
From (3.60) we have ,
Step 2.
16 3
From (3.68) we can calculate compensation capacitor g 2π f
.
44 It should be noted that the compensation capacitor needs to be optimized again after the design procedure is complete. During simulation tweaking the compensation capacitor is required to obtain the appropriate stability. Step 3.
Using (3.62) the ID1,2 can be calculated ,
Step 4.
2
From (3.62) and (3.63) the transistor size for M1,2 can be calculated ,
4
,
,
Step 5.
From the output swing requirement (3.65), Veff5 and Veff11 must satisfy
Step 6.
Following (3.75) the output transistor Veff5 can be determined 2 3 The above Veff5 has to meet the condition in step 5. Larger L5 can be tried, a max of 2Lmin. Increase L5 provides better performance over process variation.
Step 7.
Calculate ID5 using the following 2~4
Step 8.
Calculate Veff5 from (3.75) and use (3.77) to calculateW5 2 2
Step 9.
Using (3.79) calculate the transconductance of common gate 4
45 Step 10.
Using (3.80) calculate the current in the common gate amplifier
Step 11.
From step 8 and (3.81) the common gate transistor M6 can be calculated
4
3.7 Figure of Merit To perform a comparison in terms of speed among the many compensation approaches independently of the particular amplifier topology, design choices, and technology, a figure of merit (FOM) that relates the load capacitance CL, the gainbandwidth product ωGBW, and the total current consumption of the amplifier ITotal has been proposed [14]. This relation is shown in Equation 3.82. Similarly a comparison for the time domain slew rate can be expressed as in Equation 3.83. Finally, a comparison is required to measure the efficiency of the amplifier in comparison to a single stage, which is expressed in Equation 3.76. .
.
/
.
FOMss represents the ratio between the gain bandwidth of the amplifier in comparison to the gain bandwidth achieved from a pure single stage (such as a common source) with the same load and having a transconductance equal to gmT (i.e., sum of each transconductance stages). Moreover, the transconductance is a key design parameter related to the power consumption and the amplifier silicon area.
46
CHAPTER 4. 4.1 Introduction This chapter discusses the design of a low power, high speed, general purpose Op Amp driving large capacitive loads, following the design procedure outline in section 3.6. The proposed Op Amp structure applies indirect feedback frequency compensation to achieve the high speed. The Op Amp employs the traditional two gain stages followed by a class A/B output stage. This approach overcomes some of the limitations of the single miller compensation which provides very low speed amplifier driving large capacitive load. With two gain stages, indirect feedback frequency compensation capacitor as small as 5 pF can be used to drive a 150 pF. As discussed in the former chapter, low power Op Amp can be designed by carefully choosing the appropriate current density and overdrive voltage to obtain maximum gm to power efficiency.
4.2 Design Example A simple two stage Op Amp as shown in Figure 4.1 was designed for the purpose of demonstrating the indirect feedback frequency compensation. The Op Amp has a fully differential first stage, and thus need a common mode feedback circuit (CMFB). The output stage is a class A/B stage to achieve a high slew rate when charging a large capacitive load of 150 pF. A standard supply independent current source is also implemented to generate the reference current. The detail of each block will be explored in the following sections. The required Op Amp specifications are mentioned in Table 4.1. The Op Amp is designed in AMI 0.5 C5N process. The process parameters are provided in Table 4.2. The design procedure illustrated in section 3.6 is used to design the Op Amp. Further optimization is performed to achieve higher performance specifications.
47
Figure 41 Two Stage Amplifier with Class A/B output stage and indirect feedback frequency compensation Table 41 Two Stage Design Op Amp Specification
Op Amp Specification Supply Voltages
± 1.25 V
Load Capacitance: CL
100 pF
Total Current
30 μA
DC gain: Ao
70 dB
Unitygain Frequency: fu
2 MHz
Phase Margin: φM
60°
Slew Rate: SR
1 V/μs
Input Common Mode Range: VCMR ± 1 V Output Swing: Vout {max,min}
± 0.5 V
Input Referred Noise
15 nV/√Hz
48 Table 42 AMI 0.5 C5N Process Parameters
Process Parameters (AMI 0.5 Micron C5N) Parameters
NMOS
PMOS
458
212
V V
0.7
0.9
T
6.95
6.95
µ cm Vsec
nm
Table 43: Transistor Sizing for Indirect Feedback Op Amp
Op Amp Sizing Transistor Multiplier Size (μm) M1,2
2
4.05/0.9
M3,4
2
3.6/2.4
M5
6
10.05/1.5
M6
12
15/1.05
M7
6
1.65/1.05
M9,b11
10
1.65/4.05
Mb1
1
1.65/4.05
Mb2
1
1.65/1.05
Mb3
12
1.65/1.05
Mb4
1
2.4/1.05
Mb5
1
12/1.05
Mb6
12
12/1.05
Mb7
2
3/1.2
Mb8
1
1.65/1.05
Mb9,10
10
1.95/0.6
Cc

5 pF
Isupply

1.25uA
49 Complete schematic of the amplifier along with the bias generator is attached in Appendix A. It is important to have some insight while designing the bias transistors in Figure 41. The next two section provide some insight in designing the bias generator and the sizing the bias transistors.
4.2.1 Bias Generator Figure 42 depicts a supply independent bias generator used in this Op Amp design. The key idea behind supply independent biasing is that if Iout is to be completely independent of Vdd, then Iref can be a replica of Iout. In Figure 42 it can be observes that each diode connected device feeds from a current source, and thus
Vdd M5 W L
Iout and Iref are relatively independent of VDD. The
M6 W L
P
derivation of the architecture in Figure 42 is P
completed in [razavi]. The Iout from the bias generator is then expressed in Equation 4.1
W L
M3
M4
Iref
P
2
P
·
1
1
1 √
.
Iout
W L
It can be observed from the above expression, K
W L
W L
N
M1
M2
Rs Vss 42 Supply Independent Bias Generator
N
the current is independent of the supply voltage; however it is still function of process and temperature. The sizing of the bias generator is available in Appendix A.
50
4.2.2 Bias Transistor Sizing The bias transistor Mb5,6 and Mb9,10 need to be correctly biased as the set quiescent dc voltage for the output transistor M5. From step 5 of the design procedure, the overdrive voltage of the output transistor is known. The overdrive voltage Veff5 is required to be the same on Mb5, 6 and Mb9, 10 for setting the appropriate dc quiescent voltage. 2
.
.
2
.
,
4.3 Simulation Results This section expands on the simulation results obtained from the indirect feedback frequency compensation technique. Figure 43 shows the open loop frequency response of the amplifier. The unity gain frequency is at 2.01 MHz, and the corresponding the phase margin is 61˚. The amplifier behaves as a two pole system with one non dominant pole. The open loop gain achieved 72 dB. Figure 44 depicts the large signal transient response. As the phase margin is ample, there is marginal overshoot and the transient settling is quick as well. The slew rate achieved during charging and discharging are 1.262V/μs and 2.44V/μs respectively. Figure 45 shows the closed loop response of the amplifier with the different closed loop gains. The summary of the all the specifications are reported in Table 44.
51
Figure 43 AC Frequency Response of Indirect Feedback Compensation Amplifier
Figure 44 Large Signal Transient Response of Indirect Feedback Compensation Amplifier
52
Figure 45 Closed Loop Transient Response of Indirect Feedback Compensated Amplifier Table 44 Simulated Results for Indirect Feedback Compensated Amplifier
Simulated Results Specification
Specifications
Simulation
DC gain: Ao
70 dB
72.45 dB
UnityGain
2 MHz
2.01 MHz
Phase Margin: φM
60°
61.83°
Slew Rate: SR+/
± 1 V/μs
1/2.45 V/μs
± 0.5 V
1.1/0.75 V
±1V
1.14/1.1

30 μA

75 μW
Frequency: fu
Input Common Mode Range: VCMR + / VCMR= Output Swing: Vout MAX/Vout MIN ITotal Power
53 The achieved performance of the amplifier meets the required specifications in Table 41. However it is still important to verify the mathematical derivation developed in Chapter 3. Table 45 lists the relevant transconductance and parasitic values used during calculation and the achieved values during simulation. While Table 46 compares the pole locations predicted by Equations 3.203.24 and the simulation. Table 45 Relevant Design Parameters
Relevant Design Parameters Parameter
Equation
gm1
16 3
,
Design Procedure 98 μA/V
Calculated using Simulation 99 μA/V
Simulated 102 μA/V
C1
2 3
0.40 pF
0.401 pF
0.401 pF
Cc
g 2π f
7.8 pF
5.0 pF
5.0 pF
112 μA/V
174 μA/V
159.6 μA/V
681 μA/V
435 μA/V
399 μA/V


435 μA/V
gm5 gm6(Requirement)
4
gm6 (Achieved)
Table 46 Pole and Zero Locations obtained during Simulation
Comparison of Pole Locations Specification Equation
Calculated using Simulation
Simulated
Percentage Error
544 Hz
524.77 Hz
3.66 %
P2
2.218 MHz
2.184 MHz
1.55 %
z1
11.38 MHz
11.1 MHz
2.52 %
6.756 MHz
7.771 MHz
P1
P3
1
1 
13.06 %
54 From the above two tables it can be confirmed the mathematical insight developed in Chapter 3 agree to the simulation results The percentage error for the predicted location of the dominant pole and non dominant pole (p1 and p2) and the left half plane zero are small.
4.4 Alternative Indirect Feedback Compensation Scheme Results In section 3.3 and 3.4 alternative ways for implementing indirect feedback were presented. Section 3.3 routes the indirect feedback to the low impedance node between the current source and cascode node on the PMOS side. While Section 3.4 has the compensation capacitor connected to the low impedance node between the input pair and cascode node on the NMOS side. The schematics with complete transistor sizing are available in Appendix A. Table 4.7 shows the result achieved from the two architectures and compares it to the indirect feedback to a separate common gate stage amplifier in Figure 41.
Table 47 Comparison of Alternative Feedback Compensation
Comparison of Alternative Indirect Feedback Compensation Specification
Common Gate Cascode NMOS Cascode PMOS
DC gain: Ao
72.45 dB
91.1 dB
86.1 dB
UnityGain Frequency: fu 2.01 MHz
1.99 MHz
2.2 MHz
Phase Margin: φM
61.29˚
61.7˚
61.83˚
Table 47 verifies the alternative architectures achieve the same performance but with a higher gain as the cascode connections increase the output impedance of the amplifier. The cascoded indirect feedback saves area as the common gate amplifier is embedded inside the cascode connection. The cascode compensation thus is a better alternative, however the degree of freedom in choosing the transconductance of the cascode transistor gets limited.
55
4.5 Performance Comparison to Miller Compensation and Single Stage Amplifiers The proposed amplifier performance is compared to the most standard miller compensation technique. Miller compensation as explained in section 2.4.2 relies on pole splitting method for achieving closed loop stability. The technique thus significantly narrows the bandwidth of the amplifier. As the scheme boosts of bandwidth of extension, it therefore also becomes necessary to compare the performance of the indirect feedback technique to a single stage amplifier employing the same total current and transconductance. Table 48 summarizes the comparisons. Table 48 Comparison to Miller Compensated and Single Stage Amplifiers
Comparison with Miller Compensation and Single Stage Amplifiers Specification
Single Stage 36.93 dB
Single Miler Compensation 70.45 dB
Indirect Feedback Compensation 72.45
DC gain: Ao UnityGain Frequency: fu Phase Margin: φM
1.098 MHz
209.1 KHz
2.01 MHz
90˚
60.29˚
61.7˚
Cc Required
NA
35 pF
5 pF
Observing Table 48 it can be noticed that the indirect feedback compensation outperforms both the single stage architecture and miller compensated amplifiers. In comparison to miller compensation the indirect feedback achieves 10 times higher speed and simultaneously 7 times less area based on the compensation capacitor area. Further the technique even achieves twice the speed in comparison to single stage amplifiers. The increased bandwidth extension is achieved primarily due to the large ratio between the compensation capacitor (Cc) and the parasitic capacitor (C1) as observed in equation 3.23. The technique is extremely fruitful for large capacitive loads as the ratio of Cc/C1 is larger in such cases.
56
4.6 Performance Comparison to Literature The performance of the proposed threestage Op Amp topologies is compared with the ones reported in the literature. A set of figure of merits (FoMs) have been defined earlier in section 3.7 to compare various twostage topologies. Table 49 presents a comprehensive comparison of the twostage Op Amp topologies reported in literature using FoM’s described earlier. As it can be seen in Table 48, the indirect compensated two stage Op Amps outperform all other Op Amps reported in literature in gain bandwidth metric IFOMs. These Op Amps also exhibit much higher slew rate metric than most of the other amplifiers. One can also observe that the proposed Op Amps have been designed with much lower power consumption when compared to the reported Op Amp in Table 49, and yet achieve the highest speeds and fast large signal transient response. The proposed procedure thus reveals the true potential of the two stage amplifiers. Table 49 Comparison of Two Stage Op Amp Topologies
Conference
Author
Total Id (mA) GBW (MHz) Slew Rate (V/μs) Cl (pf)
IFOMs (MHz•pf)/mA IFOML ((V/μs)•pf)/mA
ECCTD ‐2007 [25]
Pennisi
1.950
TCAS ‐ 2005 [24]
700.00
2000.00
0.3
107.69
307.69
Mahattanakul 0.076
5.00
6.00
5
330.69
396.83
WESEAS ‐2006 [26]
Franz
12.800
1060.00
863.00
4
331.25
269.69
JCSC 2008 [27]
Hamed
7.667
300.00
‐NA‐
8.5
332.61
‐NA‐
JSSC ‐ 1995 [28]
Kovacs
0.110
4.50
‐NA‐
10
409.09
‐NA‐
AICSP ‐ 2009 [29]
Pugliese
0.318
27.10
25.00
10
851.71
785.71
TCAS ‐ 1997 [6]
Palumbo
0.158
28.00
6.59
5
886.08
208.54
E‐Letter 2007 [30]
Pugliese
0.032
6.70
1.00
10
2125.96
317.31
ECCTD ‐ 2005 [31]
Loikkanen
0.210
6.80
6.40
200
6476.19
6095.24
TCAS ‐ 2008 [18]
Palumbo
0.150
9.89
‐NA‐
100
6593.33
‐NA‐
This Work ‐ Cascode NMOS Kumar
0.025
1.99
1.50
100
7960.00
6000.00
This Work ‐ Common Gate Kumar This Work ‐ Cascode PMOS Kumar
0.025 0.025
2.00 2.20
2.00 2.00
100 100
8000.00 8800.00
8000.00 8000.00
57
4.7 Layout This prototype design of the indirect feedback frequency compensation is implemented in AMI 0.5μm CMOS process, and will be fabricated through MOSIS research run. In analog design, matching is very important. Particularly, Op Amps need high matching to achieve low input referred offset and high noise rejection. The matching between transistors is mainly dependent on •
Size of transistors
•
Shape of transistors
•
Orientation of transistors In general large transistors have more accurate matching than small transistors since
the large gate area reduces the impact of localized variation, long channel transistors have better matching than short channel since longer channel alleviate linewidth variation and channel modulation effects. Transistors placed in the same orientation have more precise matching than those in different direction. There in thus design, larger transistors are sized with length of 1μm and smaller transistors are sized with length 2μm to obtain larger gate area. Symmetrical layout is necessity for analog mixed signal designs, and thus all stages in this Op Amp are laid out symmetrically. The output source follower and common gate stage consume the most power and thus produce thermal gradients. To avoid unbalanced effects to the input differential pair, they are placed across the thermal line by the weighted power distribution. Power and ground buses are compromised of several metal layers and a wide cross section of buses is chosen to lower resistance and keep the voltage consistent. Dummy segments are placed as required to improve matching.
58 Floor planning is an essential step before layout as it helps to consider some of the issues mentioned above. Figure 46 shows the floor plan for the proposed Op Amp. As seen the transistors are placed across the thermal line to manage thermal gradients generated. The output and common gate transistors consume the highest power, and are thus placed across the thermal line by their weighted power distribution. The signal path runs through the middle of the layout guarded by any noise from the supplies. The input differential pair is placed on the center of the die and is laid out in a common centroid cross coupled nature to reduce 2nd order gradient effects. Wide power buses are placed above and below for easy routing to PMOS and NMOS transistors. Figure 47 shows the layout for the amplifier.
Figure 46 Floor planning for two stage amplifier with indirect feedback frequency compensation
59
Figure 47 Layout of Two Stage Op Amp with Indirect Feedback Compensation
60
CHAPTER 5. CONCLUSIONS AND FUTURE WORK In this thesis, compensation methods for Op Amps are investigated along with their pros and cons in order for a designer to choose the appropriate scheme for a particular application. This thesis further explores a creative indirect feedback compensation method which overcomes the major drawback of bandwidth narrowing by the widely used polesplitting method. It can improve the phase margin as well as extend the bandwidth of the Op Amp. The indirect feedback method can be easily applied to the existing popular two gain stage Op Amp architectures with very little alteration. The mathematical derivation and circuit simulation demonstrate the advanced properties and improved performance of this feedforward compensation technique. The indirect feedback technique discussed in this thesis is a practical and superior compensation scheme for Op Amps, and results in amplifiers with much higher speeds and smaller areas. The design procedure proposed in this thesis provides simple step by step instructions in designing such an amplifier. The two stage Op Amp designed as a part of this work achieved extremely high performance in comparison to the state of art research works. The amplifier achieved 2 MHz gain bandwidth product while driving a large 100 pF load while using only 30 μA of current. In comparison to the simple miller compensation, the achieved GBW is 10 times larger, and the compensation capacitor is 7 times smaller thus requiring a much smaller area. The Op Amp achieves even two times higher GBW in compared to single stage amplifier with the same total current and total transconductance. The technique promises great potential in achieving high speed at low power. As a part of future research the compensation method developed for the two stage amplifier can be extended to realize a three stage and multistage amplifiers. A formal derivation and design
61 procedure for multi stage amplifier employing can be developed using the indirect feedback frequency compensation technique. Indirect feedback frequency compensation technique provides a compatible low voltage, low power Op Amp design which can be used to construct high performance data converters, analog filters and other signal processing blocks in the modern sub micron CMOS process. The technique presented in this thesis should facilitate the integration of analog circuits in the modern low power high speed applications.
62
APPENDIX A. Schematics
Figure 51 Two Stage Op Amp with Common Gate Indirect Feedback Frequency Compensation
63
Figure 52 Two Stage Op Amp with Indirect Feedback Frequency Compensation to PMOS cascode node
64
Figure 53 Two Stage Op Amp with Indirect Feedback Frequency Compensation to differential pair (NMOS) cascode node
65
BIBLIOGRAPHY [1]
"Overall Roadmap Technology Characteristics (ORTC)," 03/19/2009, 2009;
http://www.itrs.net/Links/2005ITRS/ExecSum2005.pdf. [2]
D. R. Welland, S. M. Phillip, K. Y. Leung et al., “A Digital Read/Write
Channel with EEPR4 Detection,” 1994 IEEE International SolidState Circuits Conference  Digest of Technical Papers, vol. 37, pp. 276277, 1994. [3]
P. R. Gray, and R. G. Meyer, Analysis and design of analog integrated
circuits, 3rd ed., New York: Wiley, 1993. [4]
R. J. v. d. Plassche, CMOS integrated analogtodigital and digitaltoanalog
converters, 2nd ed., Boston: Kluwer Academic Publishers, 2003. [5]
B. Razavi, Design of analog CMOS integrated circuits, Boston: McGrawHill,
2001. [6]
G. Palmisano, and G. Palumbo, “A compensation strategy for twostage
CMOS opamps based on current buffer,” IEEE Transactions on Circuits and Systems IFundamental Theory and Applications, vol. 44, no. 3, pp. 257262, Mar, 1997. [7]
W. C. Black, D. J. Allstot, and R. A. Reed, “A HighPerformance LowPower
CMOS Channel Filter,” IEEE Journal of SolidState Circuits, vol. 15, no. 6, pp. 929938, 1980. [8]
P. E. Allen, and D. R. Holberg, CMOS analog circuit design, 2nd ed., New
York: Oxford University Press, 2002. [9]
H. W. Bode, Network analysis and feedback amplifier design, New York,: D.
Van Nostrand company, inc., 1945. [10]
R. J. Widlar, and M. Yamatake, “A Monolothic Power OP AMP,” IEEE
Journal of SolidState Circuits, vol. 23, no. 2, pp. 527535, Apr, 1988.
66 [11]
J. E. Solomon, “Monolothic OP AMP  Tutorial Study,” IEEE Journal of
SolidState Circuits, vol. SC 9, no. 6, pp. 314332, 1974. [12]
Y. Taur, “Cmos design near the limit of scaling,” IBM Journal of Research
and Development, vol. 46, no. 2/3, pp. 10, 2002. [13]
B. K. Ahuja, “An Improved Frequency Compensation Technique for CMOS
OperationalAmplifiers,” IEEE Journal of SolidState Circuits, vol. 18, no. 6, pp. 629633, 1983. [14]
K. N. Leung, and P. K. T. Mok, “Analysis of multistage amplifierfrequency
compensation,” IEEE Transactions on Circuits and Systems IFundamental Theory and Applications, vol. 48, no. 9, pp. 10411056, Sep, 2001. [15]
H. Lee, and P. K. T. Mok, “Activefeedback frequencycompensation
technique for lowpower multistage amplifiers,” IEEE Journal of SolidState Circuits, vol. 38, no. 3, pp. 511520, 2003. [16]
E. M. Cherry, “A 100MHz 100 dB operational amplifier with multipath
nested Miller compensation structure,” IEEE Journal of SolidState Circuits, vol. 31, no. 5, pp. 753753, May, 1996. [17]
S. Pernici, G. Nicollini, and R. Castello, “A CMOS LowDistortion Fully
Differential PowerAmplifier With Double Nested Miller Compensation,” IEEE Journal of SolidState Circuits, vol. 28, no. 7, pp. 758763, Jul, 1993. [18]
A. D. Grasso, D. Marano, G. Palumbo et al., “Improved reversed nested
Miller frequency compensation technique with voltage buffer and resistor,” IEEE Transactions on Circuits and Systems IiExpress Briefs, vol. 54, no. 5, pp. 382386, 2007. [19]
X. H. Fan, C. Mishra, and E. SanchezSinencio, “Single miller capacitor
frequency compensation technique for lowpower multistage amplifiers,” IEEE Journal of SolidState Circuits, vol. 40, no. 3, pp. 584592, 2005.
67 [20]
X. H. Peng, and W. Sansen, “Transconductance with capacitances feedback
compensation for multistage amplifiers,” IEEE Journal of SolidState Circuits, vol. 40, no. 7, pp. 15141520, 2005. [21]
P. J. Hurst, S. H. Lewis, J. P. Keane et al., “Miller compensation using current
buffers in fully differential CMOS twostage operational amplifiers,” IEEE Transactions on Circuits and Systems IRegular Papers, vol. 51, no. 2, pp. 275285, 2004. [22]
A. Pugliese, F. A. Amoroso, G. Cappuccino et al., “Design approach for fast
settling twostage amplifiers employing currentbuffer Miller compensation,” Analog Integrated Circuits and Signal Processing, vol. 59, no. 2, pp. 151159, 2009. [23]
M. Kayal, and Z. Randjelovic, “Autozero differential difference amplifier,”
Electronics Letters, vol. 36, no. 8, pp. 695696, 2000. [24]
H. Mahattanakul, and J. Chutichatuporn, “Design procedure for twostage
CMOS opamp with flexible noisepower balancing scheme,” IEEE Transactions on Circuits and Systems IRegular Papers, vol. 52, no. 8, pp. 15081514, 2005. [25]
P. Monsurro, G. Scotti, A. Trifiletti et al., “Very low voltage CMOS two
stage amplifier,” 2007 European Conference on Circuit Theory and Design, Vols 13, pp. 743746, 2007. [26]
F. Schlogl, H. Dietrich et al., “Operational Amplifier with TwoStage Gain
Boost,” Proceedings of the 6th World Scientific and Engineering Academy and Society International Conference in Simulation, Modeling and Optimization, Vols 2224, pp. 482486, 2006. [27]
H. Aminzadeh, and R. Lotfi, “On the power efficiency of cascode
compensation over Miller compensation in twostage operational amplifiers,” Journal of Circuits Systems and Computers, vol. 17, no. 1, pp. 113, 2008.
68 [28]
R. J. Reay, and G. T. A. Kovacs, “An Unconditionally Stable 2Stage CMOS
Amplifier,” IEEE Journal of SolidState Circuits, vol. 30, no. 5, pp. 591594, 1995. [29]
A. Pugliese, F. A. Amoroso, G. Cappuccino et al., “Design approach for fast
settling twostage amplifiers employing currentbuffer Miller compensation,” Analog Integrated Circuits and Signal Processing, vol. 59, no. 2, pp. 151159, 2009. [30]
A. Pugliese, F. Amoroso, G. Cappuccino et al., “Settling time optimisation
for twostage CMOS amplifiers with currentbuffer Miller compensation,” Electronics Letters, vol. 43, no. 23, pp. 12571258, 2007. [31]
M. Loikkanen, and J. Kostamovaara, “Improving capacitive drive capability of
twostage op amps with current buffer,” Proceedings of the 2005 European Conference on Circuit Theory and Design, Vol 1, pp. 99102, 2005.
69
ACKNOWLEDGEMENTS This degree would not be possible without the help and guidance of my major professor, Dr. Degang Chen. I would like to thank him for helping me learn immensely in the last few semesters. Working with you has allowed me to acquire a great number of skills as an analog engineer. You are a professor I greatly respect and admire. Thank you for everything. I would also like to thank Dr. Randall Geiger and Dr. Mani Mina, for being a part of my graduate committee and all the courses I have taken with both of you over the years have been big learning curve for me. I would like to thank my dad, Mr. Vipin Kumar, and my mom, Ms. Anjali Bhatnagar for being the biggest and best influence of my life. You have opened up so many opportunities for me. I owe all my current and future success to both of you. Without you both, none of this would be possible. Thank you for all that you have done for me. I will always be grateful. I would like to thank my sister Neha Bhatnagar and brother inlaw Sankalp Mehrotra for always believing the best in me. You both have been my biggest supporter and well wishers. I would also like to thank my peers for all their help (Siva, Bharath, Jingbo, Chen, Rien, Ryan, Ben, and Vipul) I have always enjoyed our discussions about research. Your different point of view has provided me with a few insights that have led me to solve problems with research. I not only consider all of you my peers, but also my friends. And finally, I would like to extend a special thanks to my friend Tao Zeng. Thank you for all the late night discussions and projects we worked together on. Thank you for your continued support. You have always been there for me. The last few months would have been a lot more difficult if it had not been for your help. I appreciate all that you have done.